1. Field of the Invention
The present invention relates to methods for making high Q inductors and highly efficient capacitors for VLSI circuits using metal-filled via plugs.
2. Description of the Related Art
Capacitors, especially parallel plate capacitors, are one of the most important components in VLSI circuits. As shown in FIG. 1, conventional capacitors 10 include two parallel plates 12, 14 horizontally oriented, i.e., parallel to the plane of the chip, and separated by a dielectric 16. Capacitance is defined as ##EQU1## where A represents the area of one of the plates and d is the dielectric thickness between the plates and .epsilon. is the dielectric constant. To increase capacitance, one must either increase A or decrease d or both. However, with scaling to smaller geometries, increasing A is not practicable. Also, decreasing d tends to increase process complexity.
Another important component in VLSI circuits is the inductor. High quality factor (Q) inductors are very desirable especially for high frequency applications such as wireless communications. Q is defined as ##EQU2## where .omega..sub.0 is the resonant angular frequency of the inductor, R.sub.m is the resistance of metal wire, R.sub.d is the equivalent resistance due to dielectric loss and R.sub.rad is the equivalent resistance due to RF emission from the inductor, L is the inductance of a solenoid is defined as EQU L=.pi..mu.r.sup.2 n.sup.2 l
where .mu. is the permeability of the dielectric, r is the solenoid radius, l is the solenoid length and n is the number of loops per length of solenoid.
Conventionally, inductors are formed from a metal in a spiral, although circular and square inductor layouts are also known.
From the above relationships, it can be seen that Q increases with increasing L and decreasing resistance. Metal resistance R.sub.m may be decreased in spirals having different layers of metal connected in parallel through vias. Alternatively, putting a spiral in a hole etched on the substrate surface reduces R.sub.d, but such a process is relatively complicated.
Another technique for making high Q inductors is described by Merrill, et al. "Optimization of High Q Integrated Inductors for Multi-level Metal CMOS", IEEE IEDM Digest, 1995, p. 983-986. These authors describe a technique for making series coil/spiral inductors with three-layer metal CMOS processes.
In fabricating contacts and multi-layer interconnects for integrated circuit structures for CMOS technology, it is known to fill openings formed in a dielectric with metal. These processes are commonly referred to as via plug processes, but have not been used to date for fabricating other structures such as inductors or capacitors.
It remains desirable to have methods of making high Q inductors and highly efficient capacitors for use in VLSI technologies.